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JTAG Timing
18
JTAG Timing
Table 26. JTAG Timing
All frequencies
No.
Characteristics
Min
Max
Unit
116
117
118
119
120
121
122
123
124
125
TCK frequency of operation (1/(T C × 6); maximum 22 MHz)
TCK cycle time
TCK clock pulse width
TCK rise and fall times
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO high impedance
0.0
45.0
20.0
0.0
0.0
0.0
5.0
25.0
0.0
0.0
22.0
—
—
10.0
40.0
40.0
—
—
44.0
44.0
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note:
V CORE_VDD = 1.25 V ± 0.05 V; T J = –40°C to 115°C for 150 MHz; T J = 0°C to 100°C for 181 MHz; C L = 50 pF
All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
117
118
118
TCK
(Input)
V IH
V IL
V M
V M
119
119
Figure 21. Test Clock Input Timing Diagram
DSP56371 Data Sheet, Rev. 4.1
Freescale Semiconductor
55
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